Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that Juniper Networks achieved first-pass silicon success for its largest system-on-chip (SoC) design with hundreds of millions of instances on the latest FinFET process using the Cadence Voltus IC Power Integrity Solution. With the Cadence solution in place, Juniper yielded faster turnaround times and improved signoff accuracy when compared with its previous solution.
In addition to faster turnaround and improved accuracy, the Voltus IC Power Integrity Solution incorporates the industry’s first distributed processing capability that enabled the Juniper design team to efficiently run full-chip power grid integrity analysis. The Voltus IC Power Integrity Solution streamlined Juniper’s signoff process with near-linear performance scalability on hundreds of millions of instances on hundreds of machines. It also provided Juniper with full-flat analysis of complex, billion-node designs, enabling the design team to run full chip-level power signoff without having to break the chip into multiple partitions. In addition, the seamless integration with the Cadence Innovus Implementation System and the Tempus Timing Signoff Solution enabled Juniper to optimize designs and achieve design closure faster through placement IR-aware fixing, clock STA/jitter analysis and floor-planning fixing.
“Juniper designs high-performance SoCs that require accurate and fast power signoff on extra-dense, complex power grids,” said Sanjay Kumar, senior director ASIC Designs at Juniper Networks. “The Voltus IC Power Integrity Solution provided several efficiencies that enabled us to shorten the time to design closure on our largest ever switch-chip FinFET design so that we can stay in front of the competition. Given our successful, accurate silicon results, we’re planning to use the Voltus IC Power Integrity Solution for all of our advanced-node designs.”
“Ever-increasing chip size and power-grid complexity in networking, cloud computing, graphic processing and mobile communications at advanced nodes can create challenges with signoff accuracy and turnaround time,” said KT Moore, senior product management group director of the Digital & Signoff Group at Cadence. “By using the Voltus IC Power Integrity Solution and its distributed processing capability, incorporating the latest programing techniques in data structure, modeling and massively parallel processing over multiple computer servers in matrix-solver algorithms, Juniper was able to achieve its design goals without losing any accuracy.”
The Voltus IC Power Integrity Solution is a full-chip, cell-level power signoff tool that provides accurate, fast, and high-capacity analysis and optimization technologies. For more information, please visit www.cadence.com/go/voltusic.